Data-converters bridge the physical analog world to the digital domain and are widespread in all electronic components around us—cell phones, cameras, displays, touch screens, wireless transceivers, health sensors, etc. But a longstanding limitation of data-converters is the presence electronic noise—it is one of the primary factors that causes data in the digital world to lose its original pristine quality. One way to lower noise is to burn more power, but that constrains the lifetime of portable devices.
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| Chip micrograph |
Researchers at the University of California San Diego led by electrical and computer engineering Prof. Drew Hall have developed a clever circuit technique termed 'OTA-stacking' to fundamentally improve the noise-power trade-off in analog to digital converters (ADCs). Their technique is based on the concept of current-reuse where N-fold stacking enables N times lower power for the same noise, which is very substantial.
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| Somok Mondal |
Their prototype chip achieves state-of-the-art performance in the hypercompetitive data-converter space and is being presented by UC San Diego electrical and computer engineering alumnus (Ph.D. '20) Somok Mondal on Feb. 17 at the International Solid-State Circuits Conference (ISSCC), 2021—the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip.
Paper Title: 139μW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs
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